Chiplet Physical Design Engineer

NVIDIA NVIDIA · Semiconductors · Westford, MA

NVIDIA is seeking a Chiplet Physical Design Engineer to join their Networking Silicon engineering team. The role involves owning high-speed IP integration, building Chiplet floorplan layouts, defining and implementing physical design tools and flows, and gaining experience in RTL2GDS implementation. Requires 8+ years of experience in physical design, including floor planning, layout, clock tree, power grid planning, and physical verification, with familiarity with EDA tools.

What you'd actually do

  1. Be part of a cross-business-unit team and own the high-speed IP integration.
  2. Build a Chiplet floorplan layout design from early assembly/planning through implementation and signoff.
  3. Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.
  4. Define and implement efficient, high-quality Chiplet level physical design tools, flows, and methodologies.
  5. Gain hands-on experience implementing the partition-level BE design (RTL2GDS).

Skills

Required

  • BSEE / MSEE or equivalent experience
  • 8+ years experience in physical design
  • Experience in unit and top-level floor planning, bump and RDL layout, full-chip clock tree, power grid planning, and DRC/LVS.
  • In depth knowledge of physical design flows and methodologies (PNR, STA, physical verification).
  • Deep understanding of all aspects of Physical construction and Integration.
  • Knowledge in Physical Design Verification methodology LVS/DRC.
  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Nice to have

  • Great teammate
  • creative and autonomous engineer who loves a challenge

What the JD emphasized

  • 8+ years experience in physical design