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**THE ROLE: **
This technical role is AMD client Post-Silicon features IO validation and enablement at the silicon IP level up through IP, integration, and system levels on AMD client products. This individual will be primarily responsible for leading the IO chipset /UFS validation, interfacing with IP design, debug, BIOS/firmware, and platform design groups to develop, optimize and execute validation test plans for client products from pre-silicon validation plan to post-silicon bring-up/validation, debug feature issues, and maintain validation infrastructure to achieve product deliver milestones.
**THE PERSON: **
As an IO Validation Engineer, you will deliver our new client IO chipset and IP for our products. In this high visibility position, your IP/IO/PC engineering expertise will be necessary to find and resolve silicon platform issues.Need to be well self-motivated for deliveries and innovation, strong technical background on IO IP sides, also with good communication skill
**KEY RESPONSIBILITIES: **
- Define end-to-end validation strategy /plan for UFS and chipset IO across IP, integration, and platform/system levels; establish coverage goals, entry/exit criteria, and sign-off requirements.
- Plan and execute bring-up for UFS host and devices, chipset IO blocks (USB/PCIe/SATA.etc), and platform-level use cases across boot, runtime, power-state transitions, and stress/margin conditions.
- Develop and maintain automated test and AI tool, including interop/compliance suites
- Triage issues across IP/firmware/BIOS/platform layers; isolate, reproduce, and root-cause using logs, traces, and hardware instrumentation, also Collaboration with multi-functional HW and FW teams to debug and tackle complex issues
- Communicate status, risks, and recovery plans to program leadership; contribute to POR and sign-off reviews
**PREFERRED EXPERIENCE: **
- Strong understanding of x86 architecture and system‑level interactions across CPU, chipset, firmware/BIOS, and OS.
- Deep UFS domain expertise: JEDEC UFS 3.x/4.x, UFSHCI, UniPro, M‑PHY (gears/lanes, HS/PA modes, HIBERN8, power states); features such as boot LUN, HPB, WriteBooster, RPMB, error handling, and thermal throttling.
- Hands‑on post‑silicon validation at IP, integration, and system levels;
- Pre‑silicon validation/verification experience: simulation, emulation, and FPGA/prototyping; familiarity with VIP and correlating pre‑ to post‑silicon findings.
- Expert debug/root‑cause across HW, firmware/BIOS, and drivers; proficient with Windows ETL/WPP, protocol analyzers (UFS/UniPro/M‑PHY, USB, PCIe),
**ACADEMIC CREDENTIALS: **
- Bachelor’s (5+ Years) or Master’s (3+ years) degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
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This posting is for an existing vacancy.