Circuit Design Engineer - Standard Cell

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Circuit Design Engineer for their VLSI team, focusing on standard cell libraries and custom ROM modules. The role involves transistor-level circuit design, modeling, performance analysis, and verification, with collaboration across multi-functional teams to improve quality checks on libraries. Requires MS in Electrical or Computer Engineering with 3+ years of experience in advanced submicron process issues, SPICE simulation, and DRC/LVS debug.

What you'd actually do

  1. Work on the cutting edge standard cell libraries and/or custom ROM (Read Only Memory) modules in deep submicron technologies.
  2. Drive the concepts of the transistor level standard cell circuit design, modeling and performance analysis process.
  3. Lead the function and feasibility verification of new ROM designs and set up new design flows.
  4. Provide creative insights to support and enhance existing tools and flows and develop new simulations to perform design margin evaluations.
  5. Collaborate with multi-functional teams regarding opportunities to improve standard cell develop. We will improve on our quality checks on the libraries.

Skills

Required

  • MS in Electrical or Computer Engineering (or equivalent experience)
  • 3+ years of experience
  • strong background in advanced submicron process issues
  • Deep understanding of the build and verification of both conventional cell libraries and custom ROMs
  • Hands-on experience running SPICE simulation
  • capability to adapt to new simulation tools
  • Experience with running EM/IR, aging, noise, margin, and high sigma variation simulations
  • Hands-on experience of DRC/LVS debug
  • Experience of designing and optimizing flip flops, level shifters, latches, and/or custom ROMs, register files, SRAM
  • scripting language, such as, Perl, Tcl, Make

Nice to have

  • Exposure to standard cell, memory, or custom circuit development
  • RTL, logic synthesis, and familiarity with place and route
  • Prior leadership experience
  • automation methods/algorithms

What the JD emphasized

  • 3+ years of experience
  • advanced submicron process issues
  • Deep understanding of the build and verification of both conventional cell libraries and custom ROMs
  • Hands-on experience running SPICE simulation
  • Experience with running EM/IR, aging, noise, margin, and high sigma variation simulations
  • Hands-on experience of DRC/LVS debug
  • Experience of designing and optimizing flip flops, level shifters, latches, and/or custom ROMs, register files, SRAM