Circuit Silicon Correlation Dft Engineer

NVIDIA NVIDIA · Semiconductors · Bangalore, India

NVIDIA is seeking a Circuit Silicon Correlation DFT Engineer to participate in processor design and debug, focusing on silicon characterization and correlation to pre-silicon models. Responsibilities include generating ATPG patterns, RTL/gate level verification, correlating diagnosis results to design failures, and analyzing RAM circuit failure mechanisms. The role requires a strong understanding of Design-for-test (DFT), ATPG, fault simulation, and circuit fundamentals, with experience in VLSI simulation tools and scripting languages.

What you'd actually do

  1. Participate in ground breaking Processor design and debug in deep submicron technologies.
  2. Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.
  3. Responsible for generating ATPG patterns for Silicon speed path debug.
  4. RTL and gate level verification for ATPG, non-ATPG patterns.
  5. Correlating diagnosis result to map to real design failures. Root cause the same feed learnings to pre-silicon design sign off parameters.

Skills

Required

  • BSEE or MS preferred in Electrical or Electronics Engineering
  • 3+ years experience
  • Design-for-test (DFT)
  • Logic design
  • Scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation
  • RTL/gate level simulation, writing testcase and debugging
  • VLSI simulation tools (e.g., VCS)
  • Pattern generation tools (e.g., Tessent)
  • Scripting language (e.g., Python, Perl, Tcl)

Nice to have

  • Prior leadership experience
  • Basics of circuits and RAM functionality/architecture
  • Automation methods/algorithms
  • Prior experience in STA
  • Basic understanding of circuit concepts
  • Post-Silicon data gathering experience

What the JD emphasized

  • Good understanding of Design-for-test(DFT) and logic design is required.
  • Must possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
  • Must have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it.