Compute Server Platform Architect

Cerebras · Semiconductors · US and Canada Offices · Software

Cerebras is building a novel wafer-scale AI chip and associated server platform for AI training and inference. This role focuses on the server-side platform architecture, including CPU, memory, IO, and networking, to ensure predictable performance, scalability, and reliability for AI clusters. The architect will translate workload behavior into hardware requirements, develop performance models, and engage with vendors to drive platform evaluations and adoption.

What you'd actually do

  1. Own the architecture for all server roles in Cerebras clusters, including definitions of server types, configurations, and lifecycle strategy.
  2. Define and maintain server formulas (counts and ratios per CS-3 count, cluster size, and workload type) including capacity planning and headroom policy.
  3. Specify platform configurations: CPU SKU and core strategy, our vendor roadmap (e.g., AMD, Intel, ARM), memory topology (channels, DIMM type, capacity), PCIe topology and lane budgeting, NIC selection/placement, and local NVMe policy where applicable.
  4. Translate software and runtime flows into measurable hardware requirements (CPU utilization, memory bandwidth/latency, bursty IO patterns, queueing and concurrency limits) and communicate clear guardrails back to software teams.
  5. Develop performance and scaling models; validate with microbenchmarks and workload-level experiments; identify bottlenecks and drive cross-stack fixes.

Skills

Required

  • PhD. in Computer Science or Electrical/Computer Engineering and + 8 years industry experience, or Master’s/Bachelor’s in CS or EE + 10 years industry experience.
  • 5+ years of experience in server platform architecture, systems performance engineering, or large-scale infrastructure design for AI/ML, HPC, or performance-sensitive distributed systems.
  • Deep understanding of x86 server architecture: CPU microarchitecture basics, cache hierarchies, NUMA, memory controllers/channels, and memory bandwidth vs latency tradeoffs.
  • Strong Linux systems knowledge: profiling and performance analysis, scheduling and syscall overheads, memory management behavior, and practical tuning methodology.
  • Experience reasoning about high-performance IO paths, including NIC behavior at a systems level, RDMA/RoCE concepts, and NVMe performance characteristics.
  • Proven ability to create capacity and performance models and validate them empirically with a rigorous benchmarking plan.
  • Experience working directly with vendors/partners to evaluate platforms, drive issue resolution, and influence roadmaps.
  • Strong cross-functional communication skills and ability to drive technical decisions through clear tradeoff documents and reviews.
  • Familiarity with application and system software (C, C++, Python).

What the JD emphasized

  • server-side platform architecture
  • predictable performance, scalability, and reliability
  • co-designed with software
  • token-level latency, throughput, and cost efficiency
  • CPU, memory, IO, PCIe, and host-networking requirements
  • technical leadership
  • performance and scaling models
  • cross-stack fixes
  • firmware, drivers, OS, and runtime behavior