Cpu Cache Architect

AMD AMD · Semiconductors · Fort Collins, CO · Engineering

AMD is seeking a Fellow-level experienced design engineer for their Cores Organization to work on performance modeling, analysis, and microarchitecture development for next-generation CPUs and caches. The role involves developing and enhancing performance simulators, evaluating microarchitecture improvements using various methods, and improving tools for performance analysis. Collaboration with hardware and software engineers, and mentoring junior engineers are key responsibilities. Experience with C++, computer architecture, and RTL design is preferred.

What you'd actually do

  1. Collaborate with a small, dedicated team of hardware and software engineers to optimize the performance of CPUs, caches, and interconnect.
  2. Develop and enhance cycle-accurate core, cache, and SoC (System on a chip) performance simulators.
  3. Develop other simulators at different abstraction levels.
  4. Use those simulators as well as analytical methods, emulation, and post-silicon observation and experimentation to develop and evaluate microarchitecture improvements.
  5. Develop and improve tools and methodology for performance analysis of workloads.

Skills

Required

  • analytical thinking
  • problem-solving skills
  • attention to details
  • self-motivation
  • commitment to meeting deadlines
  • creativity
  • innovation
  • verbal communication skills
  • written communication skills
  • teamwork
  • BS/MS/PhD in EE, CS, CSE (or similar)
  • expertise in hardware design

Nice to have

  • C++ programming
  • scripting language capabilities
  • Computer architecture background
  • industry experience in architecting processors, caches, and interconnect
  • Familiarity with Digital RTL Design
  • Software Development
  • Verilog HDL
  • Experience writing and debugging RTL
  • Experience collaborating effectively towards the success of a project by working closely with a diverse team across disciplines

What the JD emphasized

  • pushing the envelope on chip performance
  • status quo must be challenged