Cpu Core Physical Design Engineer

Intel Intel · Semiconductors · California, Folsom, United States

This role is for a CPU Physical Design Engineer responsible for the physical design implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, static timing analysis, and power/clock distribution. The engineer will also perform verification and signoff, analyze results to improve microarchitectures, and work with EDA vendors to enhance tool capabilities. The role requires expertise in VLSI circuit design, static timing analysis, and low power design, with a focus on developing CPUs for the AI revolution.

What you'd actually do

  1. Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
  2. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  3. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  4. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
  5. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU.

Skills

Required

  • bachelor's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 2+ years of experience OR master's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 1+ years of experience
  • VLSI circuit design
  • synthesis
  • Static timing analysis
  • Low power design

Nice to have

  • x86 CPU architecture
  • Tcl/Perl/Python programming

What the JD emphasized

  • power, frequency, and area