Cpu Design Verification Engineer

Intel Intel · Semiconductors · Bangalore, India

Performs functional verification of CPU logic, develops IP verification plans, test benches, and verification environments. Executes verification plans, runs system simulation models, analyzes power and timing, and debugs issues. Collaborates with architects, RTL developers, and physical design teams. Maintains verification infrastructure and methodology. Participates in defining CPU architecture and microarchitecture features.

What you'd actually do

  1. Performs functional verification of CPU logic to ensure design will meet specification requirements.
  2. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications.
  3. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
  4. Replicates, root causes, and debugs issues in the presilicon environment.
  5. Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

Skills

Required

  • CPU architecture fundamentals
  • microarchitecture concepts
  • SystemVerilog
  • OVM/UVM
  • validation strategy development
  • debugging test failures
  • Emulation and FPGA HW platforms
  • semi randomized test generators
  • coverage driven Validation methodologies

Nice to have

  • processor verification techniques and tools
  • SystemVerilog Assertions
  • UVM methodologies
  • Functional test development using C / x86 assembly
  • verifying power management
  • cache controllers
  • virtualization
  • memory coherency
  • Client/Server centric CPU features
  • AI based methodologies in Validation
  • Python
  • Tcl
  • Perl
  • analytical problem-solving skills
  • teamwork abilities

What the JD emphasized

  • Solid understanding of CPU architecture fundamentals and microarchitecture concepts.
  • Proficiency in SystemVerilog, OVM/UVM, and validation strategy development.
  • Strong Experience in debugging test failures.
  • Exposure on Validation using Emulation and FPGA HW platforms.
  • Strong proficiency of semi randomized test generators to meet validation objectives.
  • Strong understanding of coverage driven Validation methodologies.