Cpu Design Verification Lead/engineer

Intel Intel · Semiconductors · Bangalore, India

Lead CPU Design Verification Engineer responsible for pre-silicon functional verification of CPU architectures and microarchitectures, including test bench development, simulation, emulation, and debugging. The role also involves exploring AI-based validation methodologies.

What you'd actually do

  1. Lead development of pre-silicon functional verification tests to validate CPU logic, ensuring design requirements are met.
  2. Create and execute verification plans, including IP test benches and verification environments, to confirm coverage of CPU Instruction Set Architecture and microarchitecture specifications.
  3. Define, run, and analyze Core level simulation and emulation models to identify bugs, debug issues, and root cause design failures in the presilicon environment.
  4. Implement corrective measures to resolve failing tests and improve overall design quality.
  5. Collaborate with CPU architects, RTL developers, and physical design teams to enhance verification of complex architectural and microarchitectural features.

Skills

Required

  • SystemVerilog
  • OVM/UVM
  • validation strategy development
  • debugging test failures
  • Emulation and FPGA HW platforms
  • semi randomized test generators
  • coverage driven Validation methodologies
  • CPU architecture fundamentals
  • microarchitecture concepts
  • scripting languages (Python, Tcl, or Perl)

Nice to have

  • leading and driving Verification/Validation activities across IP/SOCs
  • processor verification techniques and tools
  • SystemVerilog Assertions
  • Functional test development using C / x86 assembly
  • verifying power management, cache controllers, virtualization, memory coherency and Client/Server centric CPU features
  • AI based methodologies in Validation

What the JD emphasized

  • 8+ years of experience with a Bachelor's degree or 6+ years of experience with a Master's degree
  • Solid understanding of CPU architecture fundamentals and microarchitecture concepts
  • Proficiency in SystemVerilog, OVM/UVM, and validation strategy development
  • Strong Experience in debugging test failures
  • Exposure on Validation using Emulation and FPGA HW platforms
  • Strong proficiency of semi randomized test generators to meet validation objectives
  • Strong understanding of coverage driven Validation methodologies
  • Good hand-on understanding of bringing AI based methodologies in Validation for improving efficiency and quality