Cpu Dfd Validation Engineer

Intel Intel · Semiconductors · Penang, Malaysia

This role focuses on the validation and debug of Design-For-Debug (DFD) logic in Intel CPUs. The engineer will develop verification plans, test benches, and software solutions for pre-silicon and post-silicon environments, collaborating with architects and designers to ensure CPU reliability and functionality. The role requires expertise in System Verilog, UVM, and scripting languages like Python, Perl, and C/C++, along with a strong understanding of CPU architecture.

What you'd actually do

  1. Develop comprehensive DFD verification plans, test benches, and environments to achieve full coverage of DFD functionality against CPU microarchitecture specifications.
  2. Define and execute verification plans, run system simulation/emulation/FPGA models, analyze power and timing, and uncover bugs in the design.
  3. Develop software solution to support in-house post-silicon validation activities and external customers, and provide necessary post-silicon debug support as needed to internal validation/manufacturing and external customers
  4. Replicate, root cause, and debug issues in both pre-silicon and post-silicon environments, implementing corrective actions as needed.
  5. Collaborate with CPU architects, RTL developers, and physical design teams to ensure DFD usage models are viable for post-silicon debug usages

Skills

Required

  • System Verilog
  • UVM
  • Python
  • Perl
  • C/C++
  • CPU architecture
  • microarchitecture fundamentals
  • debugging DFx issue in pre-silicon environment
  • problem-solving
  • analytical skills

Nice to have

  • TAP (Test Access Port)
  • ASIC or FPGA design verification
  • x86 CPU designs
  • emulation/FPGA for software/application prototyping