Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Contribute to CPU front-end designs, emphasizing micro-architecture and RTL design for next generation CPU.
- Propose performance enhancing micro-architecture features with efficiency in mind. Work with architects and performance teams for trade-off studies.
- Deliver designs that meet power, performance, and area (PPA) goals with production quality.
- Interpret techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
- 3 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
- Experience with CPU microarchitecture.
Preferred qualifications:
- Experience in scripting languages like Python or Perl.
- Knowledge of high performance and low power design techniques.
- Knowledge of assertion-based formal verification.