Cpu Physical Design Engineer

Intel Intel · Semiconductors · Texas, Austin, United States

This role involves the physical design implementation of custom CPU designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. It also includes verification and signoff, working with EDA vendors, and optimizing CPU designs for power, frequency, and area. The role requires collaboration with various engineering teams and participation in methodology improvements.

What you'd actually do

  1. Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
  2. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  3. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  4. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
  5. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.

Skills

Required

  • Bachelors in Computer Engineering or Electrical Engineering or related field with 3+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related field (or higher degree) with 2+ years of relevant work experience
  • 2+ years' experience in Synthesis of a digital logic block or partition
  • Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
  • PV convergence (such as static timing and power analysis)
  • Chip physical design verification including formal equivalence, electrical rules, DRC/LVS, and Noise flow
  • TCL Scripting

Nice to have

  • Physical design best known practices concerning floor-planning, routing techniques, clock distribution
  • At least 1 Completion of Tape Out on advanced technologies
  • Static Timing Analysis, Noise analysis, and reliability verification techniques
  • RTL to GDS methodologies and formal equivalence
  • Performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements
  • Generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores
  • Working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning