Custom Soc Ip Verification Engineer

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

Seeking a Senior Custom SOC/IP Verification Engineer to verify next-generation SoC and IP solutions, focusing on cache coherency protocols and AMBA-based interconnects (AXI, ACE, CHI). The role involves developing test plans, designing testbenches, and collaborating with cross-functional teams to ensure comprehensive verification of complex memory hierarchies in high-performance ASIC designs.

What you'd actually do

  1. Responsible for ASIC design verification for various processing blocks within a SOC, with a strong focus on cache coherency protocols and complex memory hierarchies.
  2. Develop and complete test plans for cache coherency verification of ASIC-based SoCs using UVM-based environments.
  3. Design and implement constrained-random and directed System Verilog testbenches targeting multi-level cache hierarchies and interconnect fabric.
  4. Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.
  5. Drive the development of silicon and platform verification strategies and methodologies.

Skills

Required

  • B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience)
  • 8+ years of experience in ASIC verification
  • experience in cache coherency or memory subsystem verification
  • System Verilog
  • UVM methodology
  • AMBA protocols (AXI, ACE, CHI)
  • SoC architectures
  • memory models
  • CPU-cache interactions
  • Scripting languages (Python, Perl, TCL)
  • C/C++ for testbench or model integration

Nice to have

  • formal verification
  • assertion-based verification (SVA)
  • RISC-V architecture
  • ARM architecture
  • system-level cache subsystems
  • coherency modeling tools
  • verification IPs
  • emulation platforms (Palladium, Veloce)
  • GPU-based verification

What the JD emphasized

  • expertise in cache coherency protocols
  • expertise in AMBA-based interconnects
  • strong knowledge of System Verilog
  • strong knowledge of UVM methodology
  • strong background with AMBA protocols