Ddr Lead Verification Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for a Lead Verification Engineer at AMD, focusing on planning, building, and executing verification for Memory Controller IP. It involves collaborating with architects and hardware engineers, building test plans, writing and debugging verification tests, and ensuring coverage requirements are met. Experience with memory controllers and ASIC verification is preferred.

What you'd actually do

  1. Collaborate with architects, hardware engineers to understand the new features to be verified
  2. Build test plan documentation, accounting for interactions with other features
  3. Estimate the time required to write the new feature tests and any required changes to the test environment
  4. Build the directed and random verification tests
  5. Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues
  6. Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Skills

Required

  • IP level ASIC verification
  • Debugging RTL code using simulation tools
  • ASIC design verification experience
  • Developing complex UVC
  • Coverage planning, coding, and coverage closure
  • Developing testplan at module level/IP level /Chip-level project
  • Mentoring Juniors
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • memory controllers
  • dfi
  • dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM)
  • ddr phys
  • Scripting language experience: Perl, Ruby, Makefile, shell
  • Exposure to leadership or mentorship