Ddr Phy Ams Engineer

AMD AMD · Semiconductors · Boxborough, MA · Engineering

AMD is seeking a DDR PHY AMS Engineer to support the definition, specification, system simulation, and implementation of future LPDDR IPs. The role focuses on circuit architecture and design of high-speed analog and digital blocks, calibration algorithms, equalization, and developing models for link performance simulations. The candidate will have a strong track record in Memory Phys and High-speed IOs with successful tape-outs and productization, analytical thinking, and effective communication skills.

What you'd actually do

  1. Contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHY
  2. Design circuits for High Speed IOs that include Transmitter, Receiver – CTLE/DFE, Delay Lines, DAC, OpAmp, Comparator and voltage regulators
  3. Work closely with other teams to port design to different nodes while improving the overall PPA from previous generation
  4. Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
  5. Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.

Skills

Required

  • Memory Phys
  • High-speed IOs
  • circuit architecture
  • design implementation
  • low power blocks
  • area efficient circuits
  • Transmitter design
  • Receiver design
  • CTLE/DFE
  • Delay Lines
  • DAC
  • OpAmp
  • Comparator
  • voltage regulators
  • PPA improvement
  • link-level statistical performance simulation
  • Link Training
  • PHY
  • DRAM
  • DB/RCD
  • DFE training
  • Transmit Equalization
  • micro-architecture documentation
  • algorithm documentation
  • Analog Mixed Signal design
  • Digital Design
  • Firmware
  • Verification
  • RTL
  • FW code

Nice to have

  • Matlab/Simulink
  • Verilog/AMS
  • leading junior engineers
  • signal integrity
  • power integrity

What the JD emphasized

  • strong experience building Memory Phys and High-speed IOs with track record of multiple successful Tape-out and productization
  • analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
  • strong/effective communication skills
  • enthusiastic team-first mentality
  • proven successful track record in circuit-architecture and modeling for High Speed Ios
  • proven track record of leading junior engineers to deliver complex circuits
  • Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
  • Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
  • Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).