Design Engineer – AI Soc Development

Intel Intel · Semiconductors · California, Folsom, United States +3

This role is for an RTL Design Engineer focused on developing logic design, RTL coding, and simulation for AI System-on-Chip (SoC) development. The engineer will integrate IP blocks, define architecture and microarchitecture, and optimize logic for power, performance, area, and timing. The role involves close collaboration with verification teams, physical design teams, and IP providers, and supports silicon bring-up and validation. While the products power AI applications, the core craft of the role is hardware design (RTL, SoC integration, timing closure) rather than AI/ML model development or deployment.

What you'd actually do

  1. Contribute to evaluation of architectural trade-offs considering features, performance, and system constraints
  2. Implement RTL in Verilog/System Verilog based on defined micro-architecture
  3. Integrate IP blocks at top level and ensure synthesis- and timing-clean design
  4. Work closely with verification teams to achieve full coverage and robust validation
  5. Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks

Skills

Required

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
  • 4+ years of experience in RTL design and implementation for ASIC/SoC development
  • Proficiency in Verilog/System Verilog for RTL coding and design
  • Experience with synthesis tools and timing closure methodologies

Nice to have

  • Understanding of clock domain crossings, power optimization, and timing closure
  • Exposure to SoC system integration and CPU subsystem design
  • Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
  • Knowledge of high-speed and low-power design techniques
  • Experience with static timing analysis (STA) tools and methodologies
  • Hands-on experience with formal verification tools and techniques
  • Basic scripting skills (Python, TCL, etc.) for automation
  • Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools
  • Ability to work in a dynamic environment and adapt to changing requirements
  • Strong problem-solving skills
  • Collaborative mindset
  • Eagerness to learn

What the JD emphasized

  • RTL design and implementation for ASIC/SoC development
  • Proficiency in Verilog/System Verilog for RTL coding and design
  • Experience with synthesis tools and timing closure methodologies