Design Verification Eng Graduate Intern

Intel Intel · Semiconductors · Shanghai, China +1

This is an internship role for a Design Verification Engineer focused on verifying the functional logic of silicon designs, ensuring alignment with architecture specifications. Responsibilities include developing verification plans, test benches, and environments, performing emulation and simulation, and debugging design issues. The role requires proficiency in SystemVerilog/Verilog and understanding of verification methodologies like OVM/UVM.

What you'd actually do

  1. Collaborate with architecture and design teams to ensure functional correctness and efficiency of silicon designs.
  2. Contribute to the development of verification plans, test benches, and the overall verification environment.
  3. Perform emulation and simulation tasks to verify designs and analyze power and performance.
  4. Identify, debug, and resolve design issues through root cause analysis and corrective measures.
  5. Learn and apply knowledge of digital design fundamentals, hardware architecture, and microarchitecture validation techniques.

Skills

Required

  • Enrollment in a Bachelor's or Master's degree program in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field.
  • Proficiency in SystemVerilog and Verilog for design and verification.
  • Understanding of advanced verification methodologies such as OVM and UVM.
  • Knowledge of digital design fundamentals and hardware simulation tools.
  • Experience with logic design and RTL development.
  • Familiarity with test environments, verification planning, and hardware validation.

Nice to have

  • Strong problem-solving abilities and analytical skills.
  • Ability to collaborate effectively in a cross-functional, team-oriented environment.
  • Enthusiasm for innovation and developing expertise in silicon design and verification.
  • Embrace AI usage and apply real-work AI applications into daily work.