Design Verification Engineer (1-year Contract)

AMD AMD · Semiconductors · OTTAWA, ON · Engineering

AMD is seeking a Design Verification Engineer for a 1-year contract role focused on chiplet technology. The role involves developing testbenches, writing test cases, analyzing coverage, debugging regressions, and deploying verification methodologies like UVM and Formal Verification. The position requires proficiency in Verilog, System Verilog, UVM, and ASIC design knowledge, with experience in scripting languages like Python.

What you'd actually do

  1. Developing testbenches and verification components such as UVCs, models, BFMs, and re-usable verification environments.
  2. Writing, modifying, and maintaining constraint-random and directed test cases and libraries in System Verilog/UVM.
  3. Analyzing functional, code, and test plan coverage.
  4. Implementing assertions, checkers, and monitors.
  5. Triaging and debugging regressions.

Skills

Required

  • Verilog
  • System Verilog
  • UVM
  • Linux
  • Windows
  • ASIC design
  • Verilog RTL code debugging
  • programming skills
  • Makefile
  • Perl
  • Python
  • Ruby

Nice to have

  • Formal Verification
  • scripting languages

What the JD emphasized

  • Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments.
  • Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools.
  • Must have excellent programming skills.
  • Must have exposure to Makefile and other scripting languages like Perl, Python and Ruby