Design Verification Engineer

OpenAI OpenAI · AI Frontier · San Francisco, CA · Scaling

OpenAI is seeking a Design Verification Engineer to ensure the functional correctness and robustness of their custom AI-native silicon and ML accelerators. The role involves owning the verification of complex hardware systems, defining verification plans, developing testbenches using SystemVerilog/UVM, driving bug analysis, and contributing to regression infrastructure. This is a hardware engineering role focused on the verification of AI-specific hardware components.

What you'd actually do

  1. Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
  2. Define verification plans based on architecture and microarchitecture specs.
  3. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
  4. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
  5. Drive bug triage, root cause analysis, and work closely with design teams on resolution.

Skills

Required

  • SystemVerilog
  • UVM
  • hardware verification
  • computer architecture concepts
  • memory and cache systems
  • coherency
  • interconnects
  • ML compute primitives

Nice to have

  • performance modeling
  • formal verification
  • emulation

What the JD emphasized

  • ensure functional correctness
  • robust design
  • complex hardware systems
  • reliable hardware