Design Verification Engineer

Microsoft Microsoft · Big Tech · Raleigh, NC +4 · Silicon Engineering

This role is for a Design Verification Engineer responsible for the pre-silicon verification and post-silicon validation of custom silicon components within Microsoft's Cloud Hardware and Infrastructure Engineering team. The engineer will work on developing verification IP, UVM components, stimulus, scoreboards, and assertions, while collaborating with various cross-functional teams to ensure design correctness and coverage closure.

What you'd actually do

  1. Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components.
  2. Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
  3. Develop Verification IP (VIP) components to verify home grown designs.
  4. Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
  5. Define and implement functional coverage and drive coverage closure.

Skills

Required

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.

Nice to have

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
  • 3+ years of pre-silicon System on Chip (SOC), chip level, subsystem or IP verification experience.
  • 3+ years of experience with verification principles, object-oriented programming, test plan development, testbench creation, stimulus generation, UVM/Open Verification Methodology (OVM), and coverage-based verification.
  • 3+ years of experience in SystemVerilog, C/C++, and scripting languages such as Python, Ruby or Perl.
  • Demonstrated experience on one or more of the following: Coherency, Caches, Fabrics, Double Data Rate (DDR) controllers, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Advanced eXtensible Interface(AXI)/Coherent Hub Interface(CHI) protocol bridges or other complex IP/blocks or subsystems.
  • Experience with a full product cycle from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff.
  • Experience creating, maintaining, or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), Formal Verification and/or C/C++.
  • Experience in automating verification processes using Python or another scripting language.

What the JD emphasized

  • pre-silicon verification
  • post-silicon validation
  • custom silicon components