Design Verification Engineer

Cerebras Cerebras · Semiconductors · India · Silicon

Cerebras Systems is seeking a Design Verification Engineer to work on their AI chip. The role involves developing and implementing verification strategies, creating reusable verification environments, and collaborating with cross-functional teams to ensure a high-quality design. The position requires strong debugging skills, knowledge of SystemVerilog, UVM, and software engineering practices, as well as scripting languages like Python or Perl. Experience with verification methodologies and tools is essential. The company builds the world's largest AI chip, offering significant AI compute power and enabling large-scale ML applications and fast inference, particularly for Generative AI.

What you'd actually do

  1. Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works for silicon.
  2. Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture.
  3. Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.
  4. Implement tests, manage regressions, gather coverage, and debug test failures.
  5. Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.

Skills

Required

  • SystemVerilog testbench
  • DPI
  • UVM
  • Object-oriented design
  • Python
  • Perl
  • Scripting languages
  • Software engineering practices
  • Verification methodologies
  • Simulators
  • Waveform viewers
  • Build and run automation
  • Coverage collection
  • Gate level simulations
  • Debugging
  • Problem-solving

Nice to have

  • Knowledge of pipelined processor architecture
  • BS or MS in Computer Science or Electrical Engineering

What the JD emphasized

  • high-quality design
  • verification strategies
  • reusable environments
  • debug test failures
  • cross-functional teams
  • Analyze and debug complex issues
  • verification infrastructure and flows
  • verification methodology and best practices
  • Deep knowledge of SystemVerilog testbench, DPI and UVM
  • Excellent programming skills and knowledge of software engineering practices including object-oriented design
  • Experience developing scalable and portable testbenches and components
  • Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations
  • Proficient in scripting languages such as Python or Perl
  • Good interpersonal skills and the ability to work as a standout colleague are a must
  • Extremely self-motivated and eager to solve problems
  • 3+ years of Design Verification experience.