Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and the Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Measure coverage to identify verification holes and to show progress towards tape-out.
Qualifications
Minimum qualifications:
- Bachelor's degree in electrical engineering, computer science, a related field, or equivalent practical experience.
- 1 year of experience with verification methodology (e.g., Universal verification methodology (UVM)).
- 1 year of experience in the verification of IP designs (e.g., IP, SoC, vector CPUs).
- Experience with SystemVerilog, SVA, and functional coverage.
Preferred qualifications:
- Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture.
- 2 years of experience with the full verification life cycle.
- Experience in low-power design verification.
- Experience developing and maintaining verification testbenches, test cases, and test environments.
- Experience in artificial intelligence/machine learning (AI/ML) accelerators or vector processing units.
- Experience with industry-standard simulators, revision control systems, and regression systems.