Dft Design Engineer, Machine Learning Acceleration

Amazon Amazon · Big Tech · Austin, TX · Software Development

This role is for a DFT Design Engineer focused on custom SoCs for AWS Machine Learning servers, specifically AWS Inferentia and Trainium systems. The engineer will define and develop DFT architectures, work with design teams, perform RTL coding and verification, and utilize DFT tools for test pattern generation and silicon debug. The role requires experience with complex SoC designs and standard DFT practices.

What you'd actually do

  1. Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
  2. Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
  3. Perform RTL coding and Verification using Verilog/System Verilog
  4. Utilize industry standard DFT tools to create high coverage and cost-effective test patterns to target advanced silicon defects
  5. Participate in Silicon debug efforts alongside ATE and System teams

Skills

Required

  • Bachelor's degree in Electrical or Communications Engineering or a related field
  • 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes
  • Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
  • Experience with automation script development
  • Verilog/System Verilog

Nice to have

  • Master's degree in Electrical or Communications Engineering or a related field
  • Practical experience developing STA constraints for DFT modes and working directly with PD teams to close timing
  • Experience with RTL coding and design verification (DV) flows
  • Experience with gate-level simulation setup and debug with SDF
  • Strong programming and scripting skills in Perl, Python or Tcl
  • Practical experience with silicon debug and yield optimization

What the JD emphasized

  • 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes
  • Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time