Dft Dv Engineer, AI Hardware

Tesla Tesla · Auto · Palo Alto, CA · Tesla AI

This role is for a DFT DV Engineer focused on AI Hardware at Tesla. The engineer will be responsible for the functional verification of DFT features for AI inference chips and supercomputer systems, ensuring test structures work correctly from RTL through silicon bring-up. The role involves developing SystemVerilog/UVM testbenches, verifying DFT features, running DV regressions, debugging failures, and correlating pre-Si testcases with ATE results. A key aspect is leveraging agentic AI flows to automate DV processes. While the role works with AI hardware and uses AI for automation, the core craft is hardware verification (DFT DV), not AI/ML model development.

What you'd actually do

  1. Develop SystemVerilog/UVM testbenches to verify DFT features — SSN, compressed scan, memory BIST, JTAG, and boundary scan at block and SoC level
  2. Verify top-level DFT features — power-on self-test, clock observation, clock stop, and scan dump
  3. Run DV regressions, analyze coverage, triage and debug failures to closure
  4. Identify design fixes and validate DFT RTL corrections
  5. Deliver pre-Si DV testcases for silicon bring-up and ATE correlation

Skills

Required

  • SystemVerilog
  • UVM
  • DFT features verification
  • SSN
  • compressed scan
  • memory BIST
  • JTAG
  • boundary scan
  • power-on self-test
  • clock observation
  • clock stop
  • scan dump
  • DV regressions
  • coverage analysis
  • failure triage
  • debug
  • RTL corrections validation
  • pre-Si testcases delivery
  • silicon bring-up
  • ATE correlation
  • agentic AI flows automation
  • post-silicon debug
  • server-class SoCs
  • formal verification methods for DFT structural checks

Nice to have

  • Electrical Engineering
  • Computer Engineering
  • equivalent experience
  • agentic AI flows

What the JD emphasized

  • DFT DV experience at block and SoC level
  • Expert-level SystemVerilog and UVM testbench development
  • Hands-on verification of SSN, compressed scan, MBIST, JTAG, and boundary scan
  • Experience delivering pre-Si testcases through silicon bring-up and ATE correlation
  • Ability to use agentic AI flows to automate DV regression and debug workflows
  • Post-silicon debug and ATE correlation experience on server-class SoCs