Dft Engineer

AMD AMD · Semiconductors · Shanghai, China · Engineering

This role is for a DFT Engineer at AMD, focusing on the definition, implementation, and verification of Design for Test (DFT) for System-on-Chip (SOC) within the Strategic Silicon Solution Business Unit. The engineer will work on cutting-edge DFT technology, participate in SOC DFT architecture definition, implement various DFT functions (SCAN, MBIST, etc.), perform verification, generate timing constraints, and assist with ATE bring-up and DFX logic.

What you'd actually do

  1. Participate in SOC full Chip DFT feature and architecture definition
  2. Responsible for DFT specification generation and review
  3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
  4. Perform verification on all DFT structures
  5. Generate DFT related timing constraints and work with PD team for timing closure

Skills

Required

  • ASIC DFT design and verification
  • ASIC design flow
  • SOC DFT feature and architecture definition
  • DFT specification generation and review
  • SCAN implementation
  • Boundary SCAN implementation
  • MBIST implementation
  • Analog Macro test logic implementation
  • DFT structure verification
  • DFT related timing constraints generation
  • DFT structural patterns generation
  • DFT functional patterns generation
  • ATE bring-up
  • ATE DFT pattern debug
  • DFX logic design and implementation

Nice to have

  • microprocessor design
  • Good English hearing, speaking, reading, and writing capabilities
  • Good communication skills

What the JD emphasized

  • Hands on working experience on ASIC DFT design and verification
  • Familiar with entire ASIC design flow