Dft Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

Senior Manager Silicon Design Engineer (SOC Lead) at AMD, responsible for driving end-to-end SOC/ASIC execution from concept to tape-out and productization. This role involves leading cross-functional teams, managing project planning, schedule, and deliverables, and ensuring successful silicon checkout and debug. The position requires extensive experience in SOC development, integration, and implementation, with a strong emphasis on leadership, problem-solving, and stakeholder management.

What you'd actually do

  1. Drive and lead end-to-end SOC/ASIC execution working with functional teams like Design, DFT, Verification, Physical Design to drive execution from concept to tape-out.
  2. Driving Silicon checkout and debug at ATE for Si bring up and taking it forward for ramp to production.
  3. Interface to System and SW engineering teams for successful product delivery to customer.
  4. Drive SOC from concept to productization.
  5. Work with business and design team on optimal development cost solution considering in die size, power, performance optimization.

Skills

Required

  • SOC integration and implementation
  • IP Integration
  • SOC fabrics
  • Voltage / Clock domain crossings
  • DFT
  • Power intent design
  • RTL Quality checks
  • Clock
  • Reset
  • Fuses
  • Synthesis
  • Timing Analysis
  • Design Partitioning
  • PPA optimization
  • PnR
  • Timing analysis
  • Floorplan convergence
  • Physical design implementation and signoff
  • ASIC execution
  • customer engagement
  • deliverables
  • ASIC execution flow
  • High-Level Architecture definition
  • SOC design activities
  • Verification aspects
  • Test plan review
  • Debug/triage
  • bottleneck resolution
  • design/implementation tools and flows
  • VCS
  • SOC Connectivity
  • Spyglass Lint/CDC/RDC
  • VCLP
  • Synthesis DC/FC
  • ICC
  • Physical design implementation/signoff tools
  • SOC architecture
  • System bus
  • IO protocol understanding
  • AXI
  • PCIe
  • Memory
  • System integration
  • multi-die methodology
  • packaging
  • yield
  • system solution
  • managing execution team
  • project planning
  • IP delivery timelines
  • deliverables
  • quality checks
  • Resource planning
  • critical path analysis
  • risks
  • mitigation plan
  • BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE

Nice to have

  • Work with a team of Architects, Hardware and Software engineers to define the High-Level Architecture.
  • Experience in working with SW team for BIOS, FW, Driver, SW stack, QA and SW release is a plus.
  • Comfort with Scripting such as Perl, shell, Python and TCL is a plus.

What the JD emphasized

  • 20+ years full-time experience in SOC development and delivery.
  • Experience of successfully leading couple of SOC execution from spec to tape-out and productization.