Dft Engineer

NVIDIA NVIDIA · Semiconductors · Hyderabad, India

NVIDIA is seeking a DFT Engineer to work on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on complex semiconductor chips. Responsibilities include design and implementation of test access mechanisms, memory BIST and scan compression, verification and silicon bringup of Scan ATPG and other DFT features, and developing and deploying DFT methodologies for next-generation products.

What you'd actually do

  1. As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression.
  2. Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
  3. In addition, you will help develop and deploy DFT methodologies for our next generation products.
  4. Be apart of innovation to strive improve the quality of DFT methods.
  5. You will also need to work with multi-functional teams to incorporate DFT features into the chip.

Skills

Required

  • 2+ Years of experience preferably in Design for testability (DFT)
  • well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design
  • Experience in RTL and Gates verification and simulation
  • familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500
  • Strong DFT knowledge in Scan ATPG, compression techniques and memory test
  • Strong analytical and problem solving skills
  • Expert coding skills in industry standard scripting languages
  • Extraordinary written and oral communication skills