Dft Engineer (atpg/scan Insertion)

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role focuses on planning, building, and executing verification of new and existing features for AMD's graphics processor IP. Responsibilities include collaborating with architects and engineers, building test plans, creating directed and random verification tests, debugging failures, and reviewing coverage metrics. The role requires proficiency in IP level ASIC verification, debugging firmware and RTL code, and experience with UVM testbenches, Verilog, System Verilog, C, and C++.

What you'd actually do

  1. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  2. Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  3. Estimate the time required to write the new feature tests and any required changes to the test environment
  4. Build the directed and random verification tests
  5. Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

Skills

Required

  • Bachelors or Masters degree in computer engineering/Electrical Engineering
  • Proficient in IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Experienced with Verilog, System Verilog, C, and C++

Nice to have

  • passion for modern, complex processor architecture, digital design, and verification
  • team player with excellent communication skills and experience collaborating with other engineers located in different sites/timezones
  • strong analytical and problem-solving skills and are willing to learn and ready to take on problems
  • graphics pipeline knowledge
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
  • Good working knowledge of SystemC and TLM with some related experience
  • Scripting language experience: Perl, Ruby, Makefile, shell preferred
  • Exposure to leadership or mentorship is an asset
  • Desirable assets with prior exposure to video codec system or other multimedia solutions
  • Proficient in using UVM testbenches and working in Linux and Windows environments

What the JD emphasized

  • no bugs in the final design