WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. **Together, we advance your career. **
THE ROLE:
The focus of this role is to plan, build, execute and deliver ATPG patterns with a mindset of First Time Right to Post Silicon teams; and also support post silicon debug and triage.
THE PERSON:
You have a passion for modern complex SoC's with DFT Architecture and ATPG in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
Collaborate with Functional and DFT Architects, Post Silicon ATE Engineers, and Engineers from other DFT functions to understand patterns to be developed/verfied and to prove on silicon
Build ATPG plan documentation, discuss and align on same with Architects, ATE Engineers
Estimate the time required to develop init sequences, pattern geneations using standard EDA tools and any changes required to the test generatioin and verification environment
Explore all possible opportunities, to reduce the ATE test time by delivering best optimal patterns
Debug failures both in simulation and on silicon and root cause and fix the issue; work with DFT-Design Engineers to resolve any design defects and also correct any test issues
Review overall DFT coverage; modify or add tests to get the max possible DFT coverage for each IP and for overall SoC.
PREFERRED EXPERIENCE:
Proficient in Tile and SoC level ATPG; Tile level pattern generation and SoC level pattern Retargeting
Proficient in ATPG Simulations and debugging simulation failures
Proficient in debugging failures if any on Silicon and fix the patterns quickly
Proficient in delivering high quality patterns with First Time Right approach, and make sure to have all debug patterns available for any quick debugs.
Experienced with Verilog, System Verilog, C, and C++
Proficient in Automating workflows and also using AI Agents in a distributed compute environment.
Exposure to developing and deploying AI Agents is a big plus
Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
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_Benefits offered are described: _AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
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This posting is for an existing vacancy.