Dft Engineer - Hardware

NVIDIA · Semiconductors · Bangalore, India

NVIDIA is seeking a DFT Engineer to work on groundbreaking innovations in DFT architecture, verification, and post-silicon validation for complex semiconductor chips. The role involves end-to-end DFT responsibilities from RTL design to silicon bring-up, including JTAG, boundary scan, security mechanisms, and ATPG configurations. The engineer will also develop and deploy DFT methodologies and work with multi-functional teams.

What you'd actually do

As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.
Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
In addition, you will help develop and deploy DFT methodologies for our next generation products.
Be apart of innovation to strive improve the quality of DFT methods.
You will also need to work with multi-functional teams to incorporate DFT features into the chip.

Skills

Required

BSEE or MSEE or equivalent experience
2+ years of experience
static timing Analysis
ECO
ASIC/Logic Design Flow
HDL
Digital logic design
RTL and Gates verification and simulation
BIST architecture
JTAG/IEEE1149.1/IEEE1500
Scan ATPG
compression techniques
memory test
Perl
Python

What the JD emphasized

end-to-end DFT
RTL design
Gate level scan insertion
Verification
silicon bring-up
JTAG
boundary scan
security mechanisms
test clocking
ATPG configurations
Scan ATPG
DFT features
DFT methodologies
DFT methods
DFT features
BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience
well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design
Experience in RTL and Gates verification and simulation
familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500
Strong DFT knowledge in Scan ATPG, compression techniques and memory test
Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)

Read full job description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We are looking for a DFT Engineer.

What you'll be doing:

As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.
Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
In addition, you will help develop and deploy DFT methodologies for our next generation products.
Be apart of innovation to strive improve the quality of DFT methods.
You will also need to work with multi-functional teams to incorporate DFT features into the chip.
Occasional travel and also some late hours online meetings involved during critical milestones.

What we need to see:

BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience
You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
Experience in RTL and Gates verification and simulation.
You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)

#LI-Hybrid

What you'll be doing:

As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.
Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
In addition, you will help develop and deploy DFT methodologies for our next generation products.
Be apart of innovation to strive improve the quality of DFT methods.
You will also need to work with multi-functional teams to incorporate DFT features into the chip.
Occasional travel and also some late hours online meetings involved during critical milestones.

What we need to see:

BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience
You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
Experience in RTL and Gates verification and simulation.
You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)

#LI-Hybrid