Dft Engineer - New College Grad

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a DFT Engineer to work on end-to-end Design-for-Test for sophisticated semiconductor chips, from methodology to post-silicon support. The role involves partnering with EDA tool vendors and internal teams, delivering scan features, and mentoring junior engineers. Requires knowledge in scan test plans, BIST, fault modeling, ATPG, fault simulation, and silicon debug. Experience with RTL design, STA, place-n-route, and power is beneficial.

What you'd actually do

  1. In this highly technical role, you will work on end-to-end DFT for the most sophisticated chips in the world, from methodology, to deployment to post-silicon lifecycle support.
  2. Partner with the top EDA tool vendors to develop new capabilities to support NVIDIA requirements, and with internal CAD to drive efficiency via automations.
  3. Work with NVIDIA VLSI and Operations teams to deliver the scan feature in all product segments at NVIDIA.
  4. Help mentor junior engineers on test designs and trade-offs including cost and quality.

Skills

Required

  • BSEE or MSEE (or equivalent experience)
  • Knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation.
  • Excellent analytical skills in verification and validation of test patterns and logic on sophisticated and multi-million gate designs using vendor tools.
  • Good exposure to multiple domains including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.
  • Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.

Nice to have

  • Strong programming and scripting skills in Perl, Python or Tcl

What the JD emphasized

  • Knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation.
  • Excellent analytical skills in verification and validation of test patterns and logic on sophisticated and multi-million gate designs using vendor tools.
  • Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.