Dft Lead - Atpg

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for a Silicon Design Engineer focused on Design for Test (DFT) for AMD's Radeon Technologies Group. The engineer will be responsible for implementing and verifying DFT architecture, scan insertion, ATPG pattern generation, and post-silicon support to ensure successful bring-up and yield learning. The role requires a strong understanding of DFT methodologies and experience with relevant tools and scripting languages.

What you'd actually do

  1. Implementation and verification of DFT architecture and features
  2. Scan insertion and ATPG pattern generation
  3. ATPG patterns verification with gate-level simulation
  4. Test coverage and test cost reduction analysis
  5. Post silicon support to ensure successful bring up and enhance yield learning

Skills

Required

  • Verilog RTL design
  • DFT architecture and features
  • Scan insertion
  • ATPG pattern generation
  • Gate-level simulation
  • Post silicon support
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • Design for Test methodologies
  • DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
  • Mentor testkompress and/or Synopsys Tetramax/DFTMAX
  • VCS simulation tool
  • Perl/Shell scripting