Dft - Scan/atpg Lead Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

Seeking a DFx engineer to join the CDFX team at AMD, focusing on developing and implementing cutting-edge DFx features including SCAN, ATPG, MBIST, and BSCAN for next-generation silicon innovation. The role involves close collaboration with IP Design teams, RTL designers, Verification Engineers, and the PD team to ensure correct DFT implementation and accelerate defect identification.

What you'd actually do

  1. own/lead the DFX Design Architect, Develop and implement cutting edge DFX features including SCAN, ATPG, MBIST, BSCAN, etc.
  2. Work closely with the DFX Architecture and the various IP Design teams to align on the DFX requirements and successfully implement the DFX design
  3. Design and develop correct by construction DFX design and support DFX verification
  4. Work closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects.
  5. Work with the Synthesis and PD team to ensure correct DFT implementation in Scan/ATPG.

Skills

Required

  • Experience and understanding of ASIC DFX, Scan synthesis, Integration flow using Fusion Compiler, ATPG experience in tile and SoC level experience.
  • Familiar in ICl Extraction, SSN, IJTAG,EDT, TestKompress, simulation and verification flow and experience of working in DFX architecture of complex SOC.
  • Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem
  • Experience in End-to-End DFX flow development/creation.
  • DC/AC scan (at-speed) development, debug and test.
  • Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation.
  • Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, Synopsys - Fusion compiler, Design Compiler, Spyglass
  • Experience with RTL quality check tools/methodologies such as Spyglass, Lint is required.
  • Exposure to Static timing analysis & Timing closure is required.
  • Scan/ATPG patterns & test flows development, debug, test, and characterization
  • Excellent hands-on debug skills and scripting skills are critical.
  • Strong communication skills and the ability to collaborate effectively within a global team environment are essential.
  • Strong problem-solving skills
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • Knowledge & experience of low power concepts, clock gating, power gating is a plus

What the JD emphasized

  • scripting skills are critical