Dft Verification Engineer

AMD AMD · Semiconductors · Bangalore, India · Engineering

Seeking a DFT Verification Engineer to join the server SOC DFT team, responsible for high-quality verification of DFT features for next-generation server SOCs. The role involves creating and executing test plans, verifying DFT features like JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, and high-speed IO testing at the SOC level. Responsibilities include building test benches, debugging regressions, collaborating with stakeholders, and supporting post-silicon bring-up and debug.

What you'd actually do

  1. Create and execute test plans for DFT features for next generation EPYC server SOCs.
  2. Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level.
  3. Will be creating test bench and verification infra using SV or C++.
  4. Debug regression test failures and root cause design issues, identify verification gaps and address the same.
  5. Generate patterns for post silicon testing and support ATE bring up.

Skills

Required

  • Verilog
  • C
  • C++
  • Linux
  • Windows
  • VCS
  • Verdi

Nice to have

  • Perl
  • Python
  • Ruby
  • Makefile
  • shell
  • JTAG
  • Memory BIST
  • Logic BIST
  • Scan
  • ATPG
  • post silicon debugs
  • bring up

What the JD emphasized

  • high quality verification
  • DFT features
  • next generation EPYC server SOCs
  • SOC level
  • post silicon testing
  • post silicon debugs