Dfx Methodology Architect

AMD AMD · Semiconductors · San Jose, CA · Engineering

AMD is seeking an experienced DFx Architecture, Methodology and Logic Design Expert to own and drive DFx Architecture definition, RTL implementation, and methodology development for FPGA-SoCs and custom ASICs. The role involves defining and implementing DFx features in RTL, co-owning timing and design quality checks, and working cross-functionally with various engineering teams. Experience with Siemens Tessent DFT flows and strong logic design/timing fundamentals are preferred.

What you'd actually do

  1. Define and lead SoC-DFx Architecture, Specifications and development of DFx-IPs
  2. Own DFx Architecture documentation, accounting for interactions with other features, the hardware and the firmware
  3. Implement DFx features in RTL using Verilog/SystemVerilog
  4. Co-owning Timing and Design Quality Checks (and waivers) for the DFx-IPs
  5. Work cross functionally with DFx execution and verification teams to enable integration and validation of DFx-IPs in all phases of design implementation flow

Skills

Required

  • RTL implementation
  • Verilog/SystemVerilog
  • Logic design
  • Timing
  • SoC-DFx Architecture

Nice to have

  • Siemens Tessent DFT flows
  • Tessent Shell
  • Tessent Scan
  • Tessent ATPG
  • Tessent MemoryBist
  • IJTAG
  • SSN
  • 1149.1 / 1687 standards
  • ATPG
  • 2.5D and 3D IC testing
  • DFT Architecture
  • Debug methodologies
  • Silicon debug and diagnosis
  • Perl
  • Python
  • TCL
  • Mentorship