Job Details:
Job Description:
We are seeking an experienced Director of Analog Design & Infrastructure Design Automation to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs.
The ideal candidate combines deep analog/mixed-signal design flow expertise with strong infrastructure leadership and disciplined configuration/data management practices.
Key Responsibilities
1. Analog Design Environment & Flow Management
- Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso and Custom Compiler.
- Manage PDK integration, validation, and controlled release in collaboration with foundries.
- Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC, PEX, EM/IR).
- Support simulation environments including Spectre, HSPICE, Monte Carlo, corner, and reliability analysis.
- Drive automation and methodology improvements to reduce turnaround time and increase design robustness.
2. Infrastructure & Compute Management
- Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM).
- Manage LSF/grid environments and job scheduling systems.
- Ensure scalability, system monitoring, high availability, and performance optimization.
- Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery.
- Maintain secure, access-controlled design environments aligned with IP protection policies.
3. Design Data, Manifest & Configuration Management
Design Data Governance
- Manage large-scale analog design libraries, hierarchical database structures, and technology libraries.
- Define backup, archival, and retention policies for tapeout-critical data.
- Implement data integrity validation and corruption prevention controls.
- Oversee distributed storage systems optimized for EDA workloads.
Manifest & Tapeout Release Management
Own creation and governance of tapeout manifests including:
- PDK versions
- Tool versions
- Extraction/verification decks
- Simulation models
- Signoff configurations
Establish reproducible environment release frameworks for analog programs.
Implement controlled qualification flows for tool/PDK upgrades prior to production rollout.
Maintain environment snapshots to ensure reproducibility and post-silicon traceability.
Support formal tapeout readiness and design signoff reviews.
Version Control & Configuration Management
Deploy and manage version control systems (Git, SVN, Perforce) for:
- CAD scripts and automation
- Methodology flows
- PDK overlays
- Verification decks
Define branching, tagging, and release strategies for multi-project and multi-node environments.
Implement dependency tracking across tools, PDKs, IP, and infrastructure.
Apply infrastructure-as-code principles where applicable.
Automation & Traceability
- Develop automated environment capture tools to log tool versions, library states, and system configurations.
- Enable reproducible simulations and environment packaging.
- Create dashboards and reporting metrics for design data health and DA service KPIs.
4. Leadership & Cross-Functional Collaboration
- Lead and mentor DA and infrastructure engineers.
- Serve as the primary interface between analog design, digital CAD, IT, and EDA vendors.
- Drive tool evaluations, upgrades, and vendor negotiations.
- Develop internal documentation, training programs, and best practices.
- Establish measurable service-level KPIs and continuously improve DA operations.
Required Skills and Experience
- Strong hands-on experience with analog design platforms such as Virtuoso and Custom Compiler.
- Deep understanding of analog layout, verification flows, PDK integration, and tapeout processes.
- Proven experience managing design data governance and tapeout manifest control.
- Strong Linux system administration and scripting skills (Python, Tcl, Shell).
- Experience with compute grid management, storage architecture, and license management.
- Expertise in version control and configuration management systems.
Preferred Skills and Experience
- Experience with advanced nodes (FinFET, GAA).
- Familiarity with cloud-based EDA deployment models.
- Knowledge of CI/CD practices applied to EDA environments.
- Experience supporting geographically distributed design teams.
- Strong budgeting and vendor management experience.
Key Competencies
- Technical depth in analog CAD methodologies
- Strong data governance and release discipline
- Strategic infrastructure planning
- Cross-functional leadership
- Process-driven execution with audit readiness mindset
Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in analog/mixed-signal design or CAD support.
- 5+ years of leadership experience.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.