Director Silicon Design Engineering

AMD AMD · Semiconductors · San Jose, CA · Engineering

Director of Silicon Design Engineering responsible for technical leadership and sign-off of Adaptive & Embedded Computing Group (AECG) device programs from conception to manufacturing release. This role involves problem-solving across the entire device development cycle, including architecture, RTL, analog design, verification, physical design, tapeout, and post-silicon validation. The position requires extensive ASIC design experience, leadership skills, and the ability to resolve inter-team technical issues.

What you'd actually do

  1. responsible for providing technical leadership to one or more Adaptive & Embedded Computing Group (AECG) device programs.
  2. have sign-off responsibility for the technical execution of device programs from conception & planning to release to manufacturing.
  3. leadership responsibilities will focus on problem solving in all aspects of the device development cycle including architecture, RTL, analog & custom design, design for test & manufacturing, verification, physical design & timing closure, physical verification, tapeout and post-silicon validation & qualification.
  4. When a problem does not clearly fall under the banner of one technical team or another it becomes the responsibility of the Chip Lead to bring expertise, experience and diplomacy together to coordinate a solution.
  5. The Chip Lead works with one or more Program Managers: The Program Manager tracks that IP and chip development milestones and deliverables are achieved as scheduled. The Chip Lead engages and resolves the problem when some aspect of the program is not meeting its planned objectives.

Skills

Required

  • ASIC design and development
  • leadership skills
  • interpersonal skills
  • problem-solving skills
  • communication skills
  • ASIC Development Lifecycle
  • leadership role
  • Electrical Engineering
  • Computer Engineering
  • semiconductor industry and products

Nice to have

  • FPGA technical experience
  • Post-silicon validation experience
  • Experience working with Product Planning and Marketing teams

What the JD emphasized

  • 15+ years of experience required in ASIC Development Lifecycle
  • 5+ years of experience in a leadership role with a semiconductor company