Eda Tools Hardware Engineer

Intel Intel · Semiconductors · California, Santa Clara, United States +3

This role focuses on developing and maintaining full-chip physical implementation flows for hardware design tools, including floor planning, integration, placement, routing, and power grid analysis. It involves enabling scalable SoC assembly and defining methodologies for hierarchical design reuse.

What you'd actually do

  1. Develop and maintain full-chip physical implementation flows including:
  2. Floor planning and partitioning strategies
  3. Hierarchical block integration
  4. Chip-level placement and routing coordination
  5. Power grid planning and analysis
  6. Clock tree synthesis (CTS) strategy integration

Skills

Required

  • Physical design fundamentals (I.e. placement, routing)
  • Clock tree synthesis (CTS)
  • Full-chip integration methodologies using Innovus
  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with 6+ years of experience; or a Master's degree with 4+ years of experience; or a PhD with 2+ years of experience

Nice to have

  • Static timing analysis (STA)
  • Power grid design and IR drop concepts
  • Experience with large SoC or multi-block design implementation flows
  • Experience scripting and automation skills in Linux environments