Electrical Engineer Fpga/asic - Level 3/4 - Dulles

Northrop Grumman Northrop Grumman · Aerospace · Dulles, VA +1 · Electrical

Electrical Engineer with expertise in FPGA/ASIC design using VHDL for space applications, requiring a Top-Secret/SCI clearance. Responsibilities include research, requirements analysis, system architecture, design, coding, test bench design, verification, synthesis, and place & route for Command and Data Handling (CD&H) products. Experience with FPGA design flow, static timing analysis, and power analysis is essential. Preferred qualifications include DSP, MATLAB, SimuLink, SystemVerilog, specific EDA tools, and board-level debug.

What you'd actually do

  1. research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and place, & route for our Command and Data Handling (CD&H) products.
  2. FPGA/ASIC for space applications.
  3. translating system requirements into programmable logic requirements, design documents, and test specifications
  4. defining architectures or team leadership

Skills

Required

  • Bachelor’s degree with 5 years of professional experience – OR – Master’s degree with 3 years of professional experience – OR – PhD with 1 year of professional experience.
  • VHDL design or Advanced /verification ​for FPGA’s
  • hands on experience with VHDL within the past 3 years
  • VHDL design for an aerospace environment or space application
  • FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis
  • translating system requirements into programmable logic requirements, design documents, and test specifications
  • defining architectures or team leadership

Nice to have

  • DSP, MATLAB, and SimuLink
  • VHDL and/or SystemVerilog design
  • Xilinx and Microchip (RTG4) devices.
  • Electronic Design Automation (EDA) Tools: Vivado, Quartus, QuestaSim.
  • Knowledgeable in FPGA physical constraints and achieving timing closure.
  • board or system level debug using test equipment such as oscilloscopes and logic analyzers.
  • Generation of Test Benches and support of formal VHDL Verification

What the JD emphasized

  • Requires an active Top-Secret/Sensitive Compartmented Information (SCI) clearance at time of application
  • Must have hands on experience with VHDL within the past 3 years
  • Well versed in VHDL design for an aerospace environment or space application