Fabric Interconnect Design Verification Engineer

Microsoft Microsoft · Big Tech · Raleigh, NC +4 · Silicon Engineering

This role is for a Fabric Interconnect Design Verification Engineer. The primary responsibilities include owning verification of complex flows, developing UVM-based verification environments, and applying random-stimulus and coverage-based techniques. A key aspect of the role involves applying generative AI solutions to verification work, with preferred qualifications including experience with AI in daily tasks. The role requires a Master's or Bachelor's degree in a relevant field with a specified number of years of experience in pre-silicon subsystem or IP verification. Security screening and export control compliance are also required.

What you'd actually do

  1. Own verification of complex flows at Fabric Interconnect or at block level
  2. Learn about the design and interact with partner teams to define verification strategies and test plans
  3. Develop UVM-based verification environments and run and debug simulations to drive quality
  4. Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
  5. Innovate to improve verification efficiency through methodologies or tools

Skills

Required

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
  • 2+ years of pre-silicon subsystem or IP verification experience.
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.

Nice to have

  • Demonstrated experience in verifying designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols
  • Understanding of cache coherency architectures and microarchitectures
  • Experience with verification for a full product cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
  • Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking
  • Aptitude for writing scripts/software with industry standard languages like Python
  • Experience applying generative AI to day-to-day tasks
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

What the JD emphasized

  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.