Firmware Architect – High-speed Interconnect (pcie / Oci)

AMD AMD · Semiconductors · Austin, TX · Engineering

This role is for a Firmware Architect at AMD, focusing on high-speed interconnects like PCIe and OCI for server platforms. The architect will define and drive firmware architecture, lead innovation in interconnect technologies, collaborate with cross-functional teams, and engage with industry standards. While the company mentions AI and AI-centric solutions, the core responsibilities of this specific role are in firmware architecture for hardware interconnects, not direct AI/ML model development or deployment.

What you'd actually do

  1. Define and drive firmware architecture for next-generation I/O interconnects, including PCIe Gen 7/8 and OCI, ensuring scalability, performance, and robustness.
  2. Lead the adoption and integration of advanced interconnect technologies, collaborating with hardware architecture and silicon teams to influence design decisions and standards alignment.
  3. Partner with system architecture, silicon design, validation, and platform software teams to deliver cohesive end-to-end solutions across pre- and post-silicon phases.
  4. Guide platform bring-up, debug, and optimization for complex I/O subsystems, ensuring high reliability and performance in production environments.
  5. Stay at the forefront of industry trends and standards (PCIe, CXL, OCI), contributing to AMD’s leadership in next-generation interconnect ecosystems.

Skills

Required

  • Firmware architecture
  • High-speed I/O
  • Interconnect technologies
  • PCIe Gen 7/8
  • Optical Component Interconnect (OCI)
  • Server platform architecture
  • Firmware design
  • System-level flows (boot, enumeration, link training, error handling)
  • Platform bring-up
  • Pre/post-silicon validation
  • Debugging complex I/O and firmware issues
  • Influencing architecture
  • Cross-organizational alignment

Nice to have

  • Emerging knowledge of PCIe Gen 7/8 and Optical Interconnect technologies
  • CPU/GPU interconnects
  • Memory hierarchy
  • High-speed signaling constraints
  • CXL
  • Communication skills

What the JD emphasized

  • Firmware Architecture Leadership
  • Interconnect Innovation
  • Cross-functional Collaboration
  • Platform Bring-up & Debug
  • Standards & Ecosystem Engagement
  • Extensive experience in firmware and system architecture with a focus on high-speed I/O and interconnect technologies.
  • Deep expertise in PCIe (Gen 4/5/6+) with strong familiarity or emerging knowledge of PCIe Gen 7/8 and Optical Interconnect technologies.
  • Proven experience in firmware design for complex hardware/software interfaces and system-level flows (boot, enumeration, link training, error handling).
  • Experience with platform bring-up, pre/post-silicon validation, and debugging complex I/Oand firmware issues.
  • Demonstrated ability to influence architecture and drive cross-organizational alignment.