Formal Verification Engineer

AMD AMD · Semiconductors · Austin, TX · Engineering

AMD is seeking a Formal Verification Engineer to join their Infinity Fabric network on-chip verification team. The role involves driving formal verification efforts on complex hardware designs using methodologies like VC Formal and JasperGold, writing SystemVerilog Assertions (SVA), and collaborating with RTL designers and architects. The position requires a strong focus on formal verification, with a minimum of 8 years of experience, and involves mentoring junior engineers. While the role supports AI/ML products, the core function is hardware verification, not AI model development.

What you'd actually do

  1. Develop and execute formal verification strategies using VC Formal and/or JasperGold for property checking (FPV), connectivity checking (CC), register verification (FRV), and sequential equivalence checking (SEQ)
  2. Write, review, and debug SystemVerilog Assertions (SVA) — including assumptions, assertions, and cover properties — to verify complex design behaviors
  3. Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning
  4. Collaborate with RTL designers and architects to define verification plans that incorporate formal methods alongside simulation-based approaches
  5. Identify and pursue opportunities to apply formal verification to new design blocks, championing a "formal-first" or "shift-left" verification strategy

Skills

Required

  • Formal verification strategies
  • VC Formal
  • JasperGold
  • property checking (FPV)
  • connectivity checking (CC)
  • register verification (FRV)
  • sequential equivalence checking (SEQ)
  • SystemVerilog Assertions (SVA)
  • abstraction techniques
  • complexity reduction strategies
  • assume-guarantee reasoning
  • RTL designers
  • architects
  • simulation-based approaches
  • scripting languages (TCL, Python, Perl)
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • mentor junior engineers
  • reusable formal verification infrastructure
  • constraint libraries
  • parameterized property templates
  • automated regression flows

What the JD emphasized

  • rigorous mathematical methods
  • subject matter expert
  • shift verification left
  • formal verification strategies
  • SystemVerilog Assertions (SVA)
  • formal proofs
  • formal methods
  • formal verification
  • formal-first
  • formal verification infrastructure
  • formal verification techniques
  • formal verification applications
  • formal verification