Fpga Engineer II

RTX RTX · Aerospace · mckinney, TX +1

FPGA Engineer II role focused on full lifecycle support of production quality FPGA designs for defense applications, including RF DSP, controls, and embedded processing. Requires VHDL coding, design verification, and experience with major FPGA vendors.

What you'd actually do

  1. Provide full lifecycle support of production quality FPGA designs for one or more major vendors and device families including: AMD (Xilinx), Altera, and Microchip (Microsemi).
  2. Generate FPGA designs for the following applications: gigabit serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.
  3. Assist with architecture development of FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS).
  4. Design and code in VHDL for reliability and maintainability.
  5. Support design verification utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage.

Skills

Required

  • Degree in Science, Technology, Engineering or Mathematics (STEM)
  • Minimum of 2 years of prior relevant experience
  • FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
  • Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
  • Hands-on experience with integration and debug of FPGA/ASIC in a lab environment
  • Experience with source code management, design reviews, and code release in a team development environment.

Nice to have

  • One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major.
  • Embedded systems design using ARM, Microblaze, or NIOS processors
  • Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
  • Constrained random verification in UVM using System Verilog
  • Experience with High Level Synthesis (HLS)
  • Experience with vector processors and/or GPUs
  • Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
  • Demonstrated ability to lead design efforts and/or small teams.

What the JD emphasized

  • U.S. citizenship is required
  • Active and existing security clearance required after day 1
  • FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)