Fpga Verification Engineer, Air Dominance and Strike

Anduril Anduril · Defense · Costa Mesa, CA · Air Dominance & Strike : Air Dominance & Strike Hardware : Electrical Engineering

FPGA Verification Engineer for flight-critical avionics on AMD (Xilinx) platforms, focusing on UVM-based methodology and coverage-driven verification. Requires SystemVerilog, object-oriented programming, and UVM expertise. Role involves architecting verification environments, developing verification plans, writing assertions, building coverage models, debugging failures, and collaborating with design engineers. Experience with DO-254 and safety standards is preferred.

What you'd actually do

  1. Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs
  2. Develop verification plans with traceability to system and hardware requirements
  3. Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks
  4. Build functional coverage models and drive code coverage analysis to closure
  5. Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs

Skills

Required

  • FPGA/ASIC verification
  • SystemVerilog
  • UVM methodology
  • SVA
  • Object-oriented programming
  • Industry simulators (Questa, VCS, Xcelium, or Vivado)
  • Git-based collaborative workflows
  • Linux development environments
  • Ability to obtain U.S. Secret security clearance

Nice to have

  • Master’s degree
  • DO-254
  • avionics verification standards for UAS
  • safety-critical verification processes
  • SVUnit
  • Formal verification
  • CDC verification tools
  • Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI
  • Verification automation scripting (Python, Tcl, Makefile)
  • SoC and ARM-based embedded platforms
  • Verification automation
  • CI/CD integration
  • Nix-based build environments

What the JD emphasized

  • DO-254
  • safety standards