Functional Verification Engineer -soc/ip

AMD AMD · Semiconductors · Hyderabad, India · Engineering

This role focuses on the functional verification of AMD's graphics processor IP, ensuring no bugs in the final design. It involves developing UVM environments, testbenches, and utilizing AI tools to enhance test suite efficiency. The role also includes formal verification, power-aware verification, and verification of high-speed bus protocols and interconnects.

What you'd actually do

  1. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  2. Develop UVM based verification environment and testbenches, automate processes and flows
  3. Use AI tools, models extensively to augment SV/UVM test suite for efficient coverage closure.
  4. Use Formal verification techiniques at SoC level verification
  5. Work on SoC UPF power aware verification

Skills

Required

  • UVM
  • Verilog
  • System Verilog
  • C
  • Linux
  • Windows
  • debug test failures
  • functional verification
  • coverage closure

Nice to have

  • cryptographic and security algorithms
  • Formal verification
  • SoC UPF power aware verification
  • SoC level Interconnects, NoC architecture designs
  • SoC Performance verification
  • DFx/ DFT infrastructure functional verification
  • ISO26262 Functional safety verification
  • multimillion gate chip designs verification

What the JD emphasized

  • no bugs in the final design