GPU Design Verification Engineer

Intel Intel · Semiconductors · California, Folsom, United States

This role is for a seasoned professional GPU Design Verification Engineer to join an IP team. Responsibilities include planning, designing complex structures, leading design and verification efforts, defining strategy, and architecting testbenches. The role requires expertise in Verilog, System Verilog, UVM, assertion-based verification, and industry standard protocols. Experience with AI tools or advanced process nodes is preferred.

What you'd actually do

  1. Planning, Designing complex architecture designs meeting all performance criteria, Verification strategies and leading complex projects and debugging.
  2. Work closely with architects and micro-architecture teams to define functional verification strategies and execute comprehensive test plans.
  3. Develop scalable and reusable IP verification plans, test benches, and architectures to meet graphics microarchitecture specifications.
  4. Independently own the development of test environments, feature verification, and functional coverage closure.
  5. Perform debugging and issue replication, root cause analysis, and corrective action in pre-silicon environments.

Skills

Required

  • Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or related field, plus 3+ years of relevant experience; or Master's degree with 2+ years of relevant experience; or PhD with 1+ years of relevant experience.
  • 4+ years in ASIC Design and verification.
  • System Verilog coding and UVM verification
  • Assertion-based verification methodologies
  • Industry standard protocols such as AMBA, PCIe, USB, etc.
  • Simulation tools (VCS, Xcelium, Questa)
  • Constrain random testing and assertions
  • Simulation debugging, code coverage closure, and functional coverage analysis.
  • Expert knowledge of the GPU pipeline
  • Mastery of Verilog, System Verilog, and Logic Synthesis for high-frequency, low-power designs
  • Thorough understanding of cache coherency, memory interfaces, etc.
  • Ability to work independently and manage complex tasks with minimal supervision.

Nice to have

  • Experience in high performance data center, AI tools or advanced process nodes.
  • Contribution to industry standards
  • Proficiency in Python or similar scripting languages
  • Familiarity with silicon bring up and post- silicon debugging.
  • Proficiency in C/ C++
  • Expertise in architecting plans for complex IP structures
  • Expert experience in the development of feature verification test benches and execution of functional coverage closure.
  • Leading teams, mentoring juniors and driving milestones.

What the JD emphasized

  • Mastery of Verilog, System Verilog, and Logic Synthesis for high-frequency, low-power designs
  • Expert experience in the development of feature verification test benches and execution of functional coverage closure.