Graduate Talent (standard Cell Library Design Engineer)

Intel Intel · Semiconductors · Penang, Malaysia

This role involves the design, development, verification, and delivery of standard cell libraries for Intel's next-generation SoCs and Intel Foundry customers, utilizing leading-edge process technologies. Responsibilities include circuit design, parasitic extraction and optimization, automation flow development, library characterization, and supporting library releases for product teams and external customers. The ideal candidate will have a degree in Electrical Engineering or a related field, knowledge of digital circuit design, familiarity with EDA tools, and scripting experience.

What you'd actually do

  1. Designing and implementing combinational, sequential, and power-management circuits targeting Intel's latest process technologies.
  2. Performing parasitic extraction and optimization to achieve best-in-class power, performance, robustness, and density.
  3. Developing automation flows for library modeling, validation, quality checking, performance and reliability verification.
  4. Characterizing libraries for timing, noise, power, variation, and generating both front-end and back-end models.
  5. Building, validating, releasing, and supporting standard cell libraries for Intel product teams and Intel Foundry customer design projects.

Skills

Required

  • Bachelor’s or Master’s degree in Electrical Engineering, VLSI, Microelectronics, or another closely related electrical field.
  • Excellent communication and interpersonal skills
  • digital circuit design, including CMOS combinational logic and sequential element design and layout.
  • Scripting experience for design automation using one or more of: TCL, Perl, Python, csh (or similar).
  • Knowledge of Linux environments and common Linux-based development tools

Nice to have

  • Familiarity with industry-standard EDA tools in one or more of the following areas: Circuit simulation, Cell characterization, Logic synthesis, Place-and-route, Physical design verification, Reliability verification