Graduate Trainee - Silicon Design Engineer

AMD AMD · Semiconductors · Penang, Malaysia · Engineering

This role focuses on developing silicon layouts for analog/mixed-signal circuits, with a key aspect being the adoption and improvement of AI tools and agentic workflows to enhance engineering productivity. The trainee will work on layout development, DRC/LVS checks, and contribute to the usage and setup of AI agents for automation.

What you'd actually do

  1. Develop layout for analog/mixed-signal circuits and run DRC/LVS checks
  2. Follow design rules and collaborate with designers to improve layout quality
  3. Support tapeout, debugging, and daily layout activities
  4. Use AI tools and agentic workflows to improve productivity
  5. Contribute to AI agent usage, including workflow and memory setup

Skills

Required

  • Bachelor’s Degree in Electrical / Electronic Engineering or related field
  • Develop layout for analog/mixed-signal circuits
  • run DRC/LVS checks
  • Use AI tools
  • agentic workflows

Nice to have

  • Exposure to IC layout or CMOS concepts
  • Familiar with Cadence Virtuoso or similar tools
  • Basic understanding of DRC/LVS
  • scripting (Python/Skill/Tcl)
  • Exposure to agentic workflow creation
  • Awareness of agentic memory creation
  • Coursework or project exposure in IC design or layout

What the JD emphasized

  • AI tools
  • agentic workflows
  • AI agent usage