Hardware Architect - Nvlink Fusion

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA +1

This role focuses on architecting next-generation NVLink Fusion AI scale-up hardware, specifically for the AI infrastructure market. It involves understanding AI applications and models, designing system-level solutions for connectivity, coherency, power, security, and memory, and working with cross-functional teams. The role requires deep knowledge of computer architecture, hardware-software codesign, and interchip communication, with a focus on performance and power optimization for AI systems.

What you'd actually do

  1. Work on groundbreaking AI scale up systems. Understand them across a range of disciplines and build holistic solutions
  2. Study the applications and models running on Nvidia hardware and their architectural implications
  3. Come up with system level solutions for connectivity, coherency, power management, security, and memory management.
  4. Understand and help drive implementation of bus protocols, networking protocols, memory access and security solutions across a range of products.
  5. Work with software, firmware, platform and multi-functional teams on system architecture.

Skills

Required

  • Master's Degree in Computer Engineering or Electrical Engineering (or equivalent experience)
  • 12+ years of relevant experience
  • Industry experience building high performance connectivity architectures
  • Experience with standard networking and bus protocols
  • Clear understanding of hardware-software codesign
  • Strong interpersonal, communication and teamwork skills
  • A drive to continuously learn and expand architectural breadth and depth
  • Excellent coding and algorithmic thinking skills

Nice to have

  • Good understanding of LLMs is a plus
  • Publications or other evidence of original chip/system architecture work is a plus

What the JD emphasized

  • AI scale up hardware
  • datacenter scale AI systems
  • AI infrastructure market
  • computer architecture
  • hardware-software codesign
  • interchip communication
  • high performance connectivity architectures
  • hardware-software codesign
  • LLMs