Hsio Validation Lead

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Validation Lead to drive the planning and execution of HSIO interfaces for GPUs, CPUs, and SoCs. This role involves functional bring-up, system-level validation, productization, and troubleshooting, requiring strong collaboration with various engineering teams and development of new methodologies to improve the silicon validation process. The ideal candidate will have extensive experience with PCIe/NVLINK/C2C protocols, signal integrity, and post-silicon validation in a lab environment, along with scripting skills for test automation.

What you'd actually do

  1. Drive the planning and execution of PCIe/NVLINK/C2C or similar HSIO interfaces across functional bring-up, system-level validation, productization, and troubleshooting for NVIDIA GPUs, CPUs, and SOCs.
  2. Drive schedule, programming guides, customer critical issues, manufacturing yield improvements, and design feedback. Investigate technically complicated HSIO bugs and help drive debug efforts across various teams
  3. Coordinate with logic design, circuit design, board design, Simulation, diagnostics, ATE, firmware, driver, and marketing teams to drive the chip into production.
  4. Develop new methodologies to improve the silicon validation process, helping meet upcoming industry standards for performance, adaptability, and safety.
  5. Ensure interoperability with connected devices and system components in sophisticated interconnect topologies.

Skills

Required

  • BS or MS in Electrical or Computer Engineering (or equivalent experience)
  • PCIe (or similar) protocol and characterization/validation methods
  • Signal integrity concepts
  • Silicon characteristics
  • High-speed/SERDES functional validation
  • Lab equipment (DSOs, BERT, Protocol/Logic analyzers)
  • Post-Si bring-up and functional validation of HSIO interfaces
  • Firmware/driver structures and their interaction with HW
  • Scripting languages (Perl, Python)

Nice to have

  • NVLINK/C2C interfaces
  • Customer critical issues
  • Manufacturing yield improvements
  • Design feedback
  • Interoperability with connected devices
  • System architects
  • Mixed-signal design
  • DGX
  • Software/firmware
  • Hardware/software quality assurance
  • Operations
  • Application engineering

What the JD emphasized

  • minimum of 8 years of relevant experience
  • In-depth understanding of PCIe (or similar) protocol and characterization/validation methods in a post-silicon environment
  • Excellent knowledge of Signal integrity concepts, Silicon characteristics, and high-speed/SERDES functional validation
  • Good knowledge of lab equipment (DSOs, BERT, Protocol/Logic analyzers) and hands-on post-Si bring-up, functional validation of HSIO interfaces
  • Understanding of firmware/driver structures and their interaction with HW.
  • Strong in scripting languages (Perl, _Python_) to write direct test/debug programs for stress and failure analysis